Top 25 Downloaded Manuscripts - 2022

• A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection
  Duy Thanh Nguyen; Tuan Nghia Nguyen; Hyun Kim; Hyuk-Jae Lee
• Physical Attack Protection Techniques for IC Chip Level Hardware Security
  Makoto Nagata; Takuji Miki; Noriyuki Miura
• Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
  Samaneh Babayan-Mashhadi; Reza Lotfi
• Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices
  Michael Gautschi; Pasquale Davide Schiavone; Andreas Traber; Igor Loi; Antonio Pullini; Davide Rossi; Eric Flamand; Frank K. Gürkaynak; Luca Benini
• Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
  Yufei Ma; Yu Cao; Sarma Vrudhula; Jae-sun Seo
• An FPGA-Based Phase Measurement System
  Jubin Mitra; Tapan K. Nayak
• Mixed-Signal Computing for Deep Neural Network Inference
  Boris Murmann
• An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power
  Riduan Khaddam-Aljameh; Pier-Andrea Francese; Luca Benini; Evangelos Eleftheriou
• Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns
  Fengbin Tu; Shouyi Yin; Peng Ouyang; Shibin Tang; Leibo Liu; Shaojun Wei
• VCO-Based Comparator: A Fully Adaptive Noise Scaling Comparator for High-Precision and Low-Power SAR ADCs
  Kentaro Yoshioka
• A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations
  Jian Chen; Wenfeng Zhao; Yuqi Wang; Yuhao Shu; Weixiong Jiang; Yajun Ha
• A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads
  Jorge Zarate-Roldan; Mengde Wang; Joselyn Torres; Edgar Sánchez-Sinencio
• Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
  Hamed Naseri; Somayeh Timarchi
• An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC
  Zule Xu; Naoki Ojima; Shuowei Li; Tetsuya Iizuka
• High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic
  Xiaocong Lian; Zhenyu Liu; Zhourui Song; Jiwu Dai; Wei Zhou; Xiangyang Ji
• Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse
  Jinwoo Kim; Gauthaman Murali; Heechun Park; Eric Qin; Hyoukjun Kwon; Venkata Chaitanya Krishna Chekuri; Nael Mizanur Rahman; Nihar Dasari; Arvind Singh; Minah Lee; Hakki Mert Torun; Kallol Roy; Madhavan Swaminathan; Saibal Mukhopadhyay; Tushar Krishna; Sung Kyu Lim
• Analog and Mixed-Signal Layout Automation Using Digital Place-and-Route Tools
  Po-Hsuan Wei; Boris Murmann
• A Low-Power High-Speed Comparator for Precise Applications
  Ata Khorami; Mohammad Sharifkhani
• Computing in Memory With Spin-Transfer Torque Magnetic RAM
  Shubham Jain; Ashish Ranjan; Kaushik Roy; Anand Raghunathan
• 8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing
  Akhilesh Jaiswal; Indranil Chakraborty; Amogh Agrawal; Kaushik Roy
• Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT
  Chung-Kuan Cheng; Chia-Tung Ho; Daeyeal Lee; Bill Lin; Dongwon Park
• An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs
  Chaoyang Zhu; Kejie Huang; Shuyuan Yang; Ziqi Zhu; Hejia Zhang; Haibin Shen
• A 12–14.5-GHz 10.2-mW −249-dB FoM Fractional-N Subsampling PLL With a High-Linearity Phase Interpolator in 40-nm CMOS
  Yan-Ting Chen; Pen-Jui Peng; Hung-Wen Lin
• Design and Implementation of Encryption/Decryption Architectures for BFV Homomorphic Encryption Scheme
  Ahmet Can Mert; Erdinç Öztürk; Erkay Savaş
• OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks
  Yunxuan Yu; Chen Wu; Tiandong Zhao; Kun Wang; Lei He
• The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology
  Florian Zaruba; Luca Benini