Top 25 Downloaded Manuscripts - 2021
- A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection
Duy Thanh Nguyen; Tuan Nghia Nguyen; Hyun Kim; Hyuk-Jae Lee - An FPGA-Based Phase Measurement System
Jubin Mitra; Tapan K. Nayak - An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power
Riduan Khaddam-Aljameh; Pier-Andrea Francese; Luca Benini; Evangelos Eleftheriou - Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices
Michael Gautschi; Pasquale Davide Schiavone; Andreas Traber; Igor Loi; Antonio Pullini; Davide Rossi; Eric Flamand; Frank K. Gürkaynak; Luca Benini - Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
Yufei Ma; Yu Cao; Sarma Vrudhula; Jae-sun Seo - Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
Samaneh Babayan-Mashhadi; Reza Lotfi - Mixed-Signal Computing for Deep Neural Network Inference
Boris Murmann - Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns
Fengbin Tu; Shouyi Yin; Peng Ouyang; Shibin Tang; Leibo Liu; Shaojun Wei - Computing in Memory With Spin-Transfer Torque Magnetic RAM
Shubham Jain; Ashish Ranjan; Kaushik Roy; Anand Raghunathan - A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads
Jorge Zarate-Roldan; Mengde Wang; Joselyn Torres; Edgar Sánchez-Sinencio - High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic
Xiaocong Lian; Zhenyu Liu; Zhourui Song; Jiwu Dai; Wei Zhou; Xiangyang Ji - 8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing
Akhilesh Jaiswal; Indranil Chakraborty; Amogh Agrawal; Kaushik Roy - FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs
Xifan Tang; Edouard Giacomin; Giovanni De Micheli; Pierre-Emmanuel Gaillardon - Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse
Jinwoo Kim; Gauthaman Murali; Heechun Park; Eric Qin; Hyoukjun Kwon; Venkata Chaitanya Krishna Chekuri; Nael Mizanur Rahman; Nihar Dasari; Arvind Singh; Minah Lee; Hakki Mert Torun; Kallol Roy; Madhavan Swaminathan; Saibal Mukhopadhyay; Tushar Krishna; Sung Kyu Lim - Three-Dimensional nand Flash for Vector–Matrix Multiplication
Panni Wang; Feng Xu; Bo Wang; Bin Gao; Huaqiang Wu; He Qian; Shimeng Yu - High-Utilization, High-Flexibility Depth-First CNN Coprocessor for Image Pixel Processing on FPGA
Steven Colleman; Marian Verhelst - Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
Hamed Naseri; Somayeh Timarchi - An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs
Chaoyang Zhu; Kejie Huang; Shuyuan Yang; Ziqi Zhu; Hejia Zhang; Haibin Shen - Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators
Shamik Kundu; Suvadeep Banerjee; Arnab Raha; Suriyaprakash Natarajan; Kanad Basu - High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture
S. Kala; Babita R. Jose; Jimson Mathew; S. Nalesh - A Blockchain-Based Privacy-Preserving Authentication Scheme for VANETs
Zhaojun Lu; Qian Wang; Gang Qu; Haichun Zhang; Zhenglin Liu - OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks
Yunxuan Yu; Chen Wu; Tiandong Zhao; Kun Wang; Lei He - NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators
Shanlin Xiao; Yuhao Guo; Wenkang Liao; Huipeng Deng; Yi Luo; Huanliang Zheng; Jian Wang; Cheng Li; Gezi Li; Zhiyi Yu - Design and Implementation of Encryption/Decryption Architectures for BFV Homomorphic Encryption Scheme
Ahmet Can Mert; Erdinç Öztürk; Erkay Savaş - The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology
Florian Zaruba; Luca Benini