Top 25 Downloaded Manuscripts - 2020

• An FPGA-Based Phase Measurement System
  Jubin Mitra; Tapan K. Nayak
• A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection
  Duy Thanh Nguyen; Tuan Nghia Nguyen; Hyun Kim; Hyuk-Jae Lee
• Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices
  Michael Gautschi; Pasquale Davide Schiavone; Andreas Traber; Igor Loi; Antonio Pullini; Davide Rossi; Eric Flamand; Frank K. Gürkaynak; Luca Benini
• Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
  Yufei Ma; Yu Cao; Sarma Vrudhula; Jae-sun Seo
• Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base
  Yuanyong Luo; Yuxuan Wang; Yajun Ha; Zhongfeng Wang; Siyuan Chen; Hongbing Pan
• Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
  Samaneh Babayan-Mashhadi; Reza Lotfi
• 8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing
  Akhilesh Jaiswal; Indranil Chakraborty; Amogh Agrawal; Kaushik Roy
• Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns
  Fengbin Tu; Shouyi Yin; Peng Ouyang; Shibin Tang; Leibo Liu; Shaojun Wei
• Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks
  Shihui Yin; Zhewei Jiang; Minkyu Kim; Tushar Gupta; Mingoo Seok; Jae-Sun Seo
• Mapping Spiking Neural Networks to Neuromorphic Hardware
  Adarsha Balaji; Anup Das; Yuefeng Wu; Khanh Huynh; Francesco G. Dell’Anna; Giacomo Indiveri; Jeffrey L. Krichmar; Nikil D. Dutt; Siebren Schaafsma; Francky Catthoor
• High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture
  S. Kala; Babita R. Jose; Jimson Mathew; S. Nalesh
• GH CORDIC-Based Architecture for Computing N th Root of Single-Precision Floating-Point Number
  Yuxuan Wang; Yuanyong Luo; Zhongfeng Wang; Qinghong Shen; Hongbing Pan
• High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic
  Xiaocong Lian; Zhenyu Liu; Zhourui Song; Jiwu Dai; Wei Zhou; Xiangyang Ji
• A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads
  Jorge Zarate-Roldan; Mengde Wang; Joselyn Torres; Edgar Sánchez-Sinencio
• OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks
  Yunxuan Yu; Chen Wu; Tiandong Zhao; Kun Wang; Lei He
• A Blockchain-Based Privacy-Preserving Authentication Scheme for VANETs
  Zhaojun Lu; Qian Wang; Gang Qu; Haichun Zhang; Zhenglin Liu
• Corrections to “Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base” [Sep 19 DOI: 10.1109/TVLSI.2019.2919557]
  Yuanyong Luo; Yuxuan Wang; Yajun Ha; Zhongfeng Wang; Siyuan Chen; Hongbing Pan
• Computing in Memory With Spin-Transfer Torque Magnetic RAM
  Shubham Jain; Ashish Ranjan; Kaushik Roy; Anand Raghunathan
• FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs
  Xifan Tang; Edouard Giacomin; Giovanni De Micheli; Pierre-Emmanuel Gaillardon
• Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator
  Daniel Neil; Shih-Chii Liu
• PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions
  Hongxi Dong; Manzhen Wang; Yuanyong Luo; Muhan Zheng; Mengyu An; Yajun Ha; Hongbing Pan
• Design of Power and Area Efficient Approximate Multipliers
  Suganthi Venkatachalam; Seok-Bum Ko
• A Low-Power High-Speed Comparator for Precise Applications
  Ata Khorami; Mohammad Sharifkhani
• Design and Implementation of Encryption/Decryption Architectures for BFV Homomorphic Encryption Scheme
  Ahmet Can Mert; Erdinç Öztürk; Erkay Savaş
• Design of ultrahigh-speed low-voltage CMOS CML buffers and latches
  P. Heydari; R. Mohanavelu