Top 25 Downloaded Manuscripts - 2019
- An FPGA-Based Phase Measurement System
Jubin Mitra; Tapan K. Nayak - Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
Yufei Ma; Yu Cao; Sarma Vrudhula; Jae-sun Seo - Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
Samaneh Babayan-Mashhadi; Reza Lotfi - Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices
Michael Gautschi; Pasquale Davide Schiavone; Andreas Traber; Igor Loi; Antonio Pullini; Davide Rossi; Eric Flamand; Frank K. Gürkaynak; Luca Benini - Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
Hamed Naseri; Somayeh Timarchi - Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns
Fengbin Tu; Shouyi Yin; Peng Ouyang; Shibin Tang; Leibo Liu; Shaojun Wei - A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection
Duy Thanh Nguyen; Tuan Nghia Nguyen; Hyun Kim; Hyuk-Jae Lee - FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs
Xifan Tang; Edouard Giacomin; Giovanni De Micheli; Pierre-Emmanuel Gaillardon - Accelerating Convolutional Neural Network With FFT on Embedded Hardware
Tahmid Abtahi; Colin Shea; Amey Kulkarni; Tinoosh Mohsenin - A Low-Power High-Speed Comparator for Precise Applications
Ata Khorami; Mohammad Sharifkhani - Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits
Xunzhao Yin; Xiaoming Chen; Michael Niemier; Xiaobo Sharon Hu - Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit
Partha Bhattacharyya; Bijoy Kundu; Sovan Ghosh; Vinay Kumar; Anup Dandapat - VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing
Arash Ardakani; François Leduc-Primeau; Naoya Onizawa; Takahiro Hanyu; Warren J. Gross - Computing in Memory With Spin-Transfer Torque Magnetic RAM
Shubham Jain; Ashish Ranjan; Kaushik Roy; Anand Raghunathan - A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads
Jorge Zarate-Roldan; Mengde Wang; Joselyn Torres; Edgar Sánchez-Sinencio - Design of ultrahigh-speed low-voltage CMOS CML buffers and latches
P. Heydari; R. Mohanavelu - Design of Power and Area Efficient Approximate Multipliers
Suganthi Venkatachalam; Seok-Bum Ko - A Two-Speed, Radix-4, Serial–Parallel Multiplier
Duncan J. M. Moss; David Boland; Philip H. W. Leong - Fast Binary Counters Based on Symmetric Stacking
Christopher Fritz; Adly T. Fam - ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration
Yun Long; Taesik Na; Saibal Mukhopadhyay - Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator
Daniel Neil; Shih-Chii Liu - Three-Dimensional nand Flash for Vector–Matrix Multiplication
Panni Wang; Feng Xu; Bo Wang; Bin Gao; Huaqiang Wu; He Qian; Shimeng Yu - Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base
Yuanyong Luo; Yuxuan Wang; Yajun Ha; Zhongfeng Wang; Siyuan Chen; Hongbing Pan - A Generic Power Management Circuit for Energy Harvesters With Shared Components Between the MPPT and Regulator
Gaurav Saini; Maryam Shojaei Baghini - High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic
Xiaocong Lian; Zhenyu Liu; Zhourui Song; Jiwu Dai; Wei Zhou; Xiangyang Ji - Extracting secret keys from integrated circuits
Daihyun Lim; J.W. Lee; B. Gassend; G.E. Suh; M. van Dijk; S. Devadas