Top 25 Downloaded Manuscripts - 2018
- An FPGA-Based Phase Measurement System
Jubin Mitra; Tapan K. Nayak - Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns
Fengbin Tu; Shouyi Yin; Peng Ouyang; Shibin Tang; Leibo Liu; Shaojun Wei - Design of Power and Area Efficient Approximate Multipliers
Suganthi Venkatachalam; Seok-Bum Ko - Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
Samaneh Babayan-Mashhadi; Reza Lotfi - VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing
Arash Ardakani; François Leduc-Primeau; Naoya Onizawa; Takahiro Hanyu; Warren J. Gross - Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
Yufei Ma; Yu Cao; Sarma Vrudhula; Jae-sun Seo - Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
Hamed Naseri; Somayeh Timarchi - An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks
Yizhi Wang; Jun Lin; Zhongfeng Wang - Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices
Michael Gautschi; Pasquale Davide Schiavone; Andreas Traber; Igor Loi; Antonio Pullini; Davide Rossi; Eric Flamand; Frank K. Gürkaynak; Luca Benini - A Fully Integrated Discrete-Time Superheterodyne Receiver
Massoud Tohidian; Iman Madadi; Robert Bogdan Staszewski - Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit
Partha Bhattacharyya; Bijoy Kundu; Sovan Ghosh; Vinay Kumar; Anup Dandapat - Accelerating Recurrent Neural Networks: A Memory-Efficient Approach
Zhisheng Wang; Jun Lin; Zhongfeng Wang - A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads
Jorge Zarate-Roldan; Mengde Wang; Joselyn Torres; Edgar Sánchez-Sinencio - VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems
Jui-Hung Hsieh; Hung-Ren Wang - Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies
Giuseppe Scotti; Davide Bellizia; Alessandro Trifiletti; Gaetano Palumbo - Computing in Memory With Spin-Transfer Torque Magnetic RAM
Shubham Jain; Ashish Ranjan; Kaushik Roy; Anand Raghunathan - Passive Noise Shaping in SAR ADC With Improved Efficiency
Yan Song; Chi-Hang Chan; Yan Zhu; Li Geng; Seng-Pan U.; Rui Paulo Martins - Application of Machine Learning for Optimization of 3-D Integrated Circuits and Systems
Sung Joo Park; Bumhee Bae; Joungho Kim; Madhavan Swaminathan - Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers
Vasileios Leon; Georgios Zervakis; Dimitrios Soudris; Kiamal Pekmestzi - Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator
Daniel Neil; Shih-Chii Liu - High Dynamic Performance Current-Steering DAC Design With Nested-Segment Structure
Wei Mao; Yongfu Li; Chun-Huat Heng; Yong Lian - Fast Binary Counters Based on Symmetric Stacking
Christopher Fritz; Adly T. Fam - A Low-Power High-Speed Comparator for Precise Applications
Ata Khorami; Mohammad Sharifkhani - Accelerating Convolutional Neural Network With FFT on Embedded Hardware
Tahmid Abtahi; Colin Shea; Amey Kulkarni; Tinoosh Mohsenin - DRAM-Based Intrinsic Physically Unclonable Functions for System-Level Security and Authentication
Fatemeh Tehranipoor; Nima Karimian; Wei Yan; John A. Chandy - Low-Power and Area-Efficient Carry Select Adder
B. Ramkumar; Harish M Kittur