Top 25 Downloaded Manuscripts - 2017
- A Fully Integrated Discrete-Time Superheterodyne Receiver
Massoud Tohidian; Iman Madadi; Robert Bogdan Staszewski - Design of Power and Area Efficient Approximate Multipliers
Suganthi Venkatachalam; Seok-Bum Ko - Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
Samaneh Babayan-Mashhadi; Reza Lotfi - Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit
Partha Bhattacharyya; Bijoy Kundu; Sovan Ghosh; Vinay Kumar; Anup Dandapat - Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns
Fengbin Tu; Shouyi Yin; Peng Ouyang; Shibin Tang; Leibo Liu; Shaojun Wei - An FPGA-Based Hardware Accelerator for Traffic Sign Detection
Weijing Shi; Xin Li; Zhiyi Yu; Gary Overett - VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing
Arash Ardakani; François Leduc-Primeau; Naoya Onizawa; Takahiro Hanyu; Warren J. Gross - VLSI Extreme Learning Machine: A Design Space Exploration
Enyi Yao; Arindam Basu - Low-Power and Area-Efficient Carry Select Adder
B. Ramkumar; Harish M Kittur - A 100-mA, 99.11% Current Efficiency; 2-mVpp Ripple Digitally Controlled LDO With Active Ripple Suppression
Michael Cheah; Debashis Mandal; Bertan Bakkaloglu; Sayfe Kiaei - Efficient FPGA Mapping of Pipeline SDF FFT Cores
Carl Ingemarsson; Petter Källström; Fahad Qureshi; Oscar Gustafsson - Application of Machine Learning for Optimization of 3-D Integrated Circuits and Systems
Sung Joo Park; Bumhee Bae; Joungho Kim; Madhavan Swaminathan - RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing
Reza Zendegani; Mehdi Kamal; Milad Bahadori; Ali Afzali-Kusha; Massoud Pedram - Streaming Elements for FPGA Signal and Image Processing Accelerators
Peng Wang; John McAllister - A 65-nm CMOS Constant Current Source With Reduced PVT Variation
Dong Wang; Xiao Liang Tan; Pak Kwong Chan - A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads
Jorge Zarate-Roldan; Mengde Wang; Joselyn Torres; Edgar Sánchez-Sinencio - A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications
Seyed Rasool Hosseini; Mehdi Saberi; Reza Lotfi - On the Implementation of Computation-in-Memory Parallel Adder
Hoang Anh Du Nguyen; Lei Xie; Mottaqiallah Taouil; Razvan Nane; Said Hamdioui; Koen Bertels - High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder
Syed Mohsin Abbas; YouZhe Fan; Ji Chen; Chi-Ying Tsui - DRAM-Based Intrinsic Physically Unclonable Functions for System-Level Security and Authentication
Fatemeh Tehranipoor; Nima Karimian; Wei Yan; John A. Chandy - Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices
Michael Gautschi; Pasquale Davide Schiavone; Andreas Traber; Igor Loi; Antonio Pullini; Davide Rossi; Eric Flamand; ; - Efficient Soft Cancelation Decoder Architectures for Polar Codes
Jun Lin; Zhiyuan Yan; Zhongfeng Wang - Power-Gated 9T SRAM Cell for Low-Energy Operation
Tae Woo Oh; Hanwool Jeong; Kyoman Kang; Juhyun Park; Younghwi Yang; Seong-Ook Jung - A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
Basant Kumar Mohanty; Pramod Kumar Meher - Time-Encoded Values for Highly Efficient Stochastic Circuits
M. Hassan Najafi; Shiva Jamali-Zavareh; David J. Lilja; Marc D. Riedel; Kia Bazargan; Ramesh Harjani - A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC
Je-Kwang Cho; Sunsik Woo