Top 25 Downloaded Manuscripts - 2016
- Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
Samaneh Babayan-Mashhadi; Reza Lotfi - Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit
Partha Bhattacharyya; Bijoy Kundu; Sovan Ghosh; Vinay Kumar; Anup Dandapat - Streaming Elements for FPGA Signal and Image Processing Accelerators
Peng Wang; John McAllister - A Low-Power Broad-Bandwidth Noise Cancellation VLSI Circuit Design for In-Ear Headphones
Hong-Son Vu; Kuan-Hung Chen - High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
Milad Bahadori; Mehdi Kamal; Ali Afzali-Kusha; Massoud Pedram - A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads
Jorge Zarate-Roldan; Mengde Wang; Joselyn Torres; Edgar Sánchez-Sinencio - Built-in Self-Calibration and Digital-Trim Technique for 14-Bit SAR ADCs Achieving ±1 LSB INL
Shankar Thirunakkarasu; Bertan Bakkaloglu - A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
Basant Kumar Mohanty; Pramod Kumar Meher - Minitaur; an Event-Driven FPGA-Based Spiking Network Accelerator
Daniel Neil; Shih-Chii Liu - A CMOS PWM Transceiver Using Self-Referenced Edge Detection
Kiichi Niitsu; Yusuke Osawa; Naohiro Harigai; Daiki Hirabayashi; Osamu Kobayashi; Takahiro J. Yamaguchi; Haruo Kobayashi - Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell
Sayeed Ahmad; Mohit Kumar Gupta; Naushad Alam; Mohd. Hasan - Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
Shiann-Rong Kuang; Kun-Yi Wu; Ren-Yao Lu - Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC
Jianwei Liu; Yan Zhu; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo da Silva Martins - Low-Power and Area-Efficient Carry Select Adder
B. Ramkumar; Harish M Kittur - A Two-Stage Large-Capacitive-Load Amplifier With Multiple Cross-Coupled Small-Gain Stages
Marco Ho; Jianping Guo; Tin Wai Mui; Kai Ho Mak; Wang Ling Goh; Hiu Ching Poon; Shi Bu; Ming Wai Lau; Ka Nang Leung - Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application
Manash Chanda; Sankalp Jain; Swapnadip De; Chandan Kumar Sarkar - A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications
Lior Atias; Adam Teman; Robert Giterman; Pascal Meinerzhagen; Alexander Fish - High-Speed; Low-Power; and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator
Kyungho Ryu; Jiwan Jung; Dong-Hoon Jung; Jin Hyuk Kim; Seong-Ook Jung - A High-Speed FPGA Implementation of an RSD-Based ECC Processor
Hamad Marzouqi; Mahmoud Al-Qutayri; Khaled Salah; Dimitrios Schinianakis; Thanos Stouraitis - Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology
Tooraj Nikoubin; Mahdieh Grailoo; Changzhi Li - A Sub-mW; Ultra-Low-Voltage; Wideband Low-Noise Amplifier Design Technique
Mahdi Parvizi; Karim Allidina; Mourad N. El-Gamal - A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell
C. B. Kushwah; S. K. Vishvakarma - Noise Modeling and Analysis of SAR ADCs
Wenpian Paul Zhang; Xingyuan Tong - Reducing Power; Leakage; and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops
Niranjan Kulkarni; Jinghua Yang; Jae-Sun Seo; Sarma Vrudhula - A Thermal Energy Harvesting Power Supply With an Internal Startup Circuit for Pacemakers
Mohammadreza Ashraf; Nasser Masoumi