Top 25 Downloaded Manuscripts - 2015
- Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
Samaneh Babayan-Mashhadi; Reza Lotfi - A CMOS PWM Transceiver Using Self-Referenced Edge Detection
Kiichi Niitsu; Yusuke Osawa; Naohiro Harigai; Daiki Hirabayashi; Osamu Kobayashi; Takahiro J. Yamaguchi; Haruo Kobayashi - Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit
Partha Bhattacharyya; Bijoy Kundu; Sovan Ghosh; Vinay Kumar; Anup Dandapat - Low-Power and Area-Efficient Carry Select Adder
B. Ramkumar; Harish M Kittur - Built-in Self-Calibration and Digital-Trim Technique for 14-Bit SAR ADCs Achieving ±1 LSB INL
Shankar Thirunakkarasu; Bertan Bakkaloglu - Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block
I-Chyn Wey; Chien-Chang Peng; Feng-Yu Liao - "Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator"
Daniel Neil; Shih-Chii Liu - Design of a Low-Voltage Low-Dropout Regulator
Chung-Hsun Huang; Ying-Ting Ma; Wei-Chen Liao - Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging
James S. Guido; Alexandre Yakovlev - An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation
Indranil Hatai; Indrajit Chakrabarti; Swapna Banerjee - Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II–Evaluation at Circuit Level and Design Perspectives
Massimo Alioto; David Esseni - Z-TCAM: An SRAM-based Architecture for TCAM
Zahid Ullah; Manish K. Jaiswal; Ray C. C. Cheung - A Highly Efficient Ultralow Photovoltaic Power Harvesting System With MPPT for Internet of Things Smart Nodes
Xiaosen Liu; Edgar Sánchez-Sinencio - An I/O Efficient Model Checking Algorithm for Large-Scale Systems
Lijun Wu; Huijia Huang; Kaile Su; Shaowei Cai; Xiaosong Zhang - CMOS Full-Adders for Energy-Efficient Arithmetic Applications
Mariano Aguirre-Hernandez; Monico Linares-Aranda - Recursive Approach to the Design of a Parallel Self-Timed Adder
Mohammed Ziaur Rahman; Lindsay Kleeman; Mohammad Ashfak Habib - Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application
Manash Chanda; Sankalp Jain; Swapnadip De; Chandan Kumar Sarkar - "A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique"
Mahdi Parvizi; Karim Allidina; Mourad N. El-Gamal - Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path
Zhengfan Xia; Masanori Hariyama; Michitaka Kameyama - VLSI Design of a Large-Number Multiplier for Fully Homomorphic Encryption
Wei Wang; Xinming Huang; Niall Emmart; Charles Weems - Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
Ing-Chao Lin; Yu-Hung Cho; Yi-Ming Yang - Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems
Qiang Liu; Terrence Mak; Tao Zhang; Xinyu Niu; Wayne Luk; Alex Yakovlev - Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications
Yu-Hsuan Lee; Cheng-Wei Pan - Architectural and Circuit Design Techniques for Power Management of Ultra-Low-Power MCU Systems
Michael Lueders; Bjoern Eversmann; Johannes Gerber; Korbinian Huber; Ruediger Kuhn; Michael Zwerg; Doris Schmitt-Landsiedel; Ralf Brederlow - A Novel Single-Inductor Dual-Input Dual-Output DC–DC Converter With PWM Control for Solar Energy Harvesting System
Hui Shao; Xing Li; Chi-Ying Tsui; Wing-Hung Ki