Top 25 Downloaded Manuscripts - 2013
- Low-Power and Area-Efficient Carry Select Adder
"Ramkumar, B.; Kittur, H.M."
- Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
"Babayan-Mashhadi, S.; Lotfi, R."
- Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops
"Shyu, Y.-T.; Lin, J.-M.; Huang, C.-P.; Lin, C.-W.; Lin, Y.-Z.; Chang, S.-J."
- Design of Testable Reversible Sequential Circuits
"Thapliyal, H.; Ranganathan, N.; Kotiyal, S."
- Constant Delay Logic Style
"Doni Lazar, K.A.G.; Vincent, A.V."
- Security-Enabled Near-Field Communication Tag With Flexible Architecture Supporting Asymmetric Cryptography
"Plos, T.; Hutter, M.; Feldhofer, M.; Stiglic, M.; Cavaliere, F."
- Glitch-Free NAND-Based Digitally Controlled Delay-Lines
"De Caro, D."
- A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks
"Liang Li; Maunder, R.G.; Al-Hashimi, B.M.; Hanzo, L. "
- 10-bit 30-MS/s SAR ADC Using a Switchback Switching Method
Guan-Ying Huang; Soon-Jyh Chang; Chun-Cheng Liu; Ying-Zu Lin
- CORDIC Designs for Fixed Angle of Rotation
"Meher, P.K.; Park, S.Y."
- CMOS Full-Adders for Energy-Efficient Arithmetic Applications
"Aguirre-Hernandez, M.; Linares-Aranda, M."
- MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems
"Yang, K.-J.; Tsai, S.-H.; Chuang, G.C.H."
- A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing
Anh-Tuan Do; Shoushun Chen; Zhi-Hui Kong; Kiat Seng Yeo
- Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms
"Whatmough, P.N.; Das, S.; Bull, D.M.; Darwazeh, I."
- Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology
"Bhoj, A.N.; Jha, N.K."
- Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic
"Absel, K.; Manuel, L.; Kavitha, R.K."
- A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering
"Hyman, R.; Ranganathan, N.; Bingel, T.; Tran Vo, D."
- Pipelined Radix-2k Feedforward FFT Architectures
"Garrido, M.; Grajal, J.; Sanchez, M.A.; Gustafsson, O."
- VLSI Architecture of Arithmetic Coder Used in SPIHT
"Liu, K.; Belyaev, E.; Guo, J."
- Formal Verification of Architectural Power Intent
"Hazra, A.; Goyal, S.; Dasgupta, P.; Pal, A."
- A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction
You-Gang Chen; Hen-Wai Tsao; Chorng-Sii Hwang
- Low-Power Correlation for IEEE 802.16 OFDM Synchronization on FPGA
"Pham, T.H.; Fahmy, S.A.; McLoughlin, I.V."
- Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs)
"Yoonmyung Lee; Daeyeon Kim; Jin Cai; Lauer, I.; Chang, L.; Koester, S.J.; Blaauw, D.; Sylvester, D. "
- Subthreshold Dual Mode Logic
"Kaizerman, A.; Fisher, S.; Fish, A."
- "Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool"
"Aksoy, L.; Lazzari, C.; Costa, E.; Flores, P.; Monteiro, J."