Top 25 Downloaded Manuscripts - 2012
- Low-Power and Area-Efficient Carry Select Adder
Ramkumar, B.; Kittur, H.M.
- A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security
Cheng, C.J.; Wang, C.C.; Ku, W.C.; Chen, T.F.; Wang, J.S.
- A 3–5 GHz Current-Reuse g_{m} -Boosted CG LNA for Ultrawideband in 130 nm CMOS
Khurram, M.; Rezaul Hasan, S.M.
- Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design
Kulkarni, J.P.; Roy, K.
- VLSI Architecture of Arithmetic Coder Used in SPIHT
Liu, K.; Belyaev, E.; Guo, J.
- Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme
Hwang, Y.T.; Lin, J.F.; Sheu, M.h.
- A Low-Power Single-Phase Clock Multiband Flexible Divider
Manthena, V.K.; Do, A.V.; Boon, C.C.; Yeo, K.S.
- UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations
Kulkarni, R.; Kim, J; Jeon, H.Y.; Xiao, J.; Silva-Martinez, J.
- CMOS Full-Adders for Energy-Efficient Arithmetic Applications
Aguirre-Hernandez, M.; Linares-Aranda, M.
- Pipelined Parallel FFT Architectures via Folding Transformation
Ayinala, M.; Brown, M; Parhi, K.K.
- Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits
Meijer, M.; de Gyvez, J.P.
- Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm
Tsao, Y.C.; Choi, K.
- AdNoC: Runtime Adaptive Network-on-Chip Architecture
Al Faruque, M.A.; Ebi, T.; Henkel, J.
- Synthesis and Array Processor Realization of a 2-D IIR Beam Filter for Wireless Applications
Joshi, R.M.; Madanayake, A. ; Adikari, J. ; Bruton, L.T.
- High-Speed Low-Power Viterbi Decoder Design for TCM Decoders
He, J.; Liu, H.; Wang, Z.; Huang, X.; Zhang; K.
- Using Magnetic RAM to Build Low-Power and Soft Error-Resilient L1 Cache
Liu, C.; Xu, W.; Zhao J.; Zheng, N.; Zhang, T.
- A Low-Power Gigabit CMOS Limiting Amplifier Using Negative Impedance Compensation and Its Application
Han; J.; Yoo, K.; Lee, D.; Park, K.; Oh, W.; Park, S.M
- Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique
Hwang, Y.T.; Lin, J.F.
- Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing
Guan, X.; Fei, Y.; Lin, H.
- Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance
Purohit, S.; Margala, M.
- A Low-Power Low-Cost Design of Primary Synchronization Signal Detection
Ma, C.; Cao, H.; Lin, P.
- A survey of design techniques for system-level dynamic power management
Benini, L.; Bogliolo, A. ; De Micheli, G.
- A 15 MHz to 600 MHz, 20 mW, 0.38 mm ^{2} Split-Control, Fast Coarse Locking Digital DLL in 0.13 \mu m CMOS
Hoyos, S.; Tsang, C.W.; Vanderhaegen, J.; Chiu, Y.; Khorramabadi, H.; Nikolic, B.
- Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling
Crupi, F.; Alioto, M. ; Franco, J. ; Magnone, P. ; Kaczer, B. ; Groeseneken, G. ; Mitard, J. ; Witters, L. ; Hoffmann, T.Y.
- A High Performance Switched Capacitor-Based DC-DC Buck Converter Suitable for Embedded Power Management Applications
Maity, B.; Mandal, P.