Top 25 Downloaded Manuscripts - 2011
- CMOS Full-Adders for Energy-Efficient Arithmetic Applications
Aguirre-Hernandez, M.; Linares-Aranda, M.
- Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM
Do, A.T.; Kong, Z.H.; Yeo, K.S.; Low, J.Y.S.
- Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops
Phyu, M.W.; Fu, K.; Goh, W.L.; Yeo, K.S.
- High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications
Wang, J.P.; Kuang, S.R.; Liang, S.C.
- Iris Biometrics for Embedded Systems
Liu-Jimenez, J.; Sanchez-Reillo, R.; Fernandez-Saavedra, B.
- Efficient Pattern Matching Algorithm for Memory Architecture
Lin, C.H.; Chang, S.C.
- Low-Power and Area-Efficient Carry Select Adder
Ramkumar, B. Kittur, H.M.
- A New VLSI Architecture of Parallel Multiplier-Accumulator Based on Radix-2 Modified Booth Algorithm
Seo, Y.H.; Kim. D.W.
- Reconfigurable SRAM Architecture With Spatial Voltage Scaling for Low Power Mobile Multimedia Applications
Cho, M.; Schlessman, J. ; Wolf, W. ; Mukhopadhyay, S.
- A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design
Joshi, R.V.; Kanj, R. ; Ramadurai, V.
- A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme
Hsu, H.J.; Huang, S.Y.
- "A Sub-1 V, 26 \mu W, Low-Output-Impedance CMOS Bandgap Reference With a Low Dropout or Source Follower Mode"
Ng, D.C.W.; Kwong, D.K.K.; Wong, N.
- A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic
Abdel-Hafeez, S.; Gordon-ross, A.
- Multilevel Power Optimization of Pipelined A/D Converters
Kim, J.; Limotyrakis, S. ; Yang, C.-K.K.
- Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines
Eshraghian, K.; Cho, K.R.; Kavehei, O.; Kang, S.K.; Kang, S.M.
- Design of ultrahigh-speed low-voltage CMOS CML buffers and latches
Heydari, P.; Mohanavelu, R.
- SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage
Mukhopadhyay, S.; Rao, R.M.; Kim, J.J.; Chuang, C.T.
- Design of Sequential Elements for Low Power Clocking System
Zhao, P.; McNeely, J.; Kuang, W.; Wang, N.; Wang, Z.
- An analytical model for predicting the remaining battery capacity of lithium-ion batteries
Rong, P.; Pedram, M.
- A CMOS Image Sensor With On-Chip Image Compression Based on Predictive Boundary Adaptation and Memoryless QTD Algorithm
Chen, S.; Bermak, A. ; Yan Wang
- Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits
Sathanur, A.; Benini, L. ; Macii, A. ; Macii, E. ; Poncino, M.
- Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies
khan, N.H.; Alam, S.M. ; Hassoun, S.
- A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor
Choi, J.; Kim, S.T. ; Woonyun Kim ; Kwan-Woo Kim ; Kyutae Lim ; Laskar, J.
- A survey of design techniques for system-level dynamic power management
Benini, L.; Bogliolo, A. ; De Micheli, G.
- FPGA Based on Integration of CMOS and RRAM
Tanachutiwat, S; Liu, M.; Wei, W.