Top 25 Downloaded Manuscripts - 2010
- A New VLSI Architecture of Parallel Multiplier-Accumulator Based on Radix-2 Modified Booth Algorithm
Seo, Y.H.; Kim. D.W.
- A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies
Yamauchi, H.
- A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme
Lin, Y.Z.; Lin, C.W.; Chang, S.J.
- Self-Repairing SRAM Using On-Chip Detection and Compensation
Mojumder, N.N.; Mukhopadhyay, S.; Kim, J.J.; Chuang, C.T.; Roy, K.
- Single- and Multi-core Configurable AES Architectures for Flexible Security
Wang, M.Y.; Su, C.P.; Horng, C.L.; Wu, C.W.; Huang, C.T
- A Low-Cost VLSI Implementation for Efficient Removal of Impulse Noise
Chen, P.Y.; Lien, C.Y.; Chuang, H.M.
- Low-Complexity Switch Network for Reconfigurable LDPC Decoders
Oh, D.; Parhi, K.K.
- Compressive Acquisition CMOS Image Sensor: From the Algorithm to Hardware Implementation
Zhang, M.; Bermak, A.
- Floating-Point FPGA: Architecture and Modeling
Ho, C.H.; Yu, C.W.; Leong, P.; Luk, W.; Wilton, S.J.E.
- Design of a CMOS Broadband Transimpedance Amplifier With Active Feedback
Lu, Z.; Yeo, K.S.; Lim, W.M.; Do, A.V.; Boon, C.C.
- CMOS Bandgap References With Self-Biased Symmetrically Matched Current-Voltage Mirror and Extension of Sub-1-V Design
Lam, Y.H.; Ki, W.H
- VLSI Implementation of BCH Error Correction for Multilevel Cell NAND Flash Memory
Choi, H.; Liu, W.; Sung, W.
- "The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis"
Wang, W.; Yang, S.; Bhardwaj, S. ; Vrudhula, S. ; Liu, T. ; Cao, Y.
- Design Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation
Habib, I.; Paker, O. ; Sawitzki, S.
- Improving FPGA Performance for Carry-Save Arithmetic
Parandeh-Afshar, H.; Verma, A.K.; Brisk, P.; Ienne, P.
- A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation
Mahalingam, V.; Bhattacharya, K. ; Ranganathan, N. ; Chakravarthula, H. ; Murphy, R.R. ; Pratt, K.S.
- On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures
Kang, K.; Park, S.P.; Kim, K.; Roy, K.
- Design and Analysis of High-Throughput Lossless Image Compression Engine Using VLSI-Oriented FELICS Algorithm
Tsai, T.H. Lee, Y.H., Lee, Y.Y.
- Reducing SRAM Power Using Fine-Grained Wordline Pulsewidth Control
Abu-Rahma, M.H.; Anis, M.; Yoon, S.S.
- Analysis and Design of a Multistage CMOS Band-Pass Low-Noise Preamplifier for Ultrawideband RF Receiver
Rezaul Hasan, S.M.
- Integrated Solar Energy Harvesting and Storage
Guilar, N.J.; Kleeburg, T.J. ; Chen, A. ; Yankelevich, D.R. ; Amirtharajah, R.
- A Low-Power DSP for Wireless Communications
Lee, H.; Chakrabarti, C.; Mudge, T.
- Characterization of Single-Electron Tunneling Transistors for Designing Low-Power Embedded Systems
Zhu, C.; Gu, Z.; Dick, R.P.; Shang, L.; Knobel, R.G.
- Power Estimation of Embedded Multiplier Blocks in FPGAs
Jevtic, R.; Carreras, C.