Top 25 Downloaded Manuscripts - 2009
- Low-Power, High-Speed Transceivers for Network-on-Chip Communication
Schinkel, D.; Mensink, E.; Klumperink, E.; van Tuijl, E.; Nauta, B.
- Integrated Solar Energy Harvesting and Storage
Guilar, N.J.; Kleeburg, T.J.; Chen, A.; Yankelevich, D.R.; Amirtharajah, R.
- Design of ultrahigh-speed low-voltage CMOS CML buffers and latches
Heydari, P.; Mohanavelu, R.
- Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating
Mahmoodi, H.; Tirumalashetty, V.; Cooke, M.; Roy, K.
- Multi-Gb/s LDPC Code Design and Implementation
Jin Sha; Zhongfeng Wang; Minglun Gao; Li Li
- Characterization of Single-Electron Tunneling Transistors for Designing Low-Power Embedded Systems
Changyun Zhu; Zhengyu Gu; Dick, R.P;. Li Shang; Knobel, R.G.
- Energy-Efficient Subthreshold Processor Design
Bo Zhai; Pant, S.; Nazhandali, L.; Hanson, S.; Olson, J.; Reeves, A.; Minuth, M.; Helfand, R.; Austin, T.; Sylvester, D.; Blaauw, D.
- High-Throughput Layered LDPC Decoding Architecture
Zhiqiang Cui; Zhongfeng Wang; Youjian Liu
- BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture
Mottaghi-Dastjerdi, M.; Afzali-Kusha, A.; Pedram, M.
- Decoding the Golden Code: A VLSI Design
Cerato, B.; Masera, G.; Viterbo, E.
- A Low-Noise Multi-GHz CMOS Multiloop Ring Oscillator With Coarse and Fine Frequency Tuning
Hai Qi Liu; Wang Ling Goh; Siek, L.; Wei Meng; Lim Yue; Ping Zhang
- Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture
Yoonjin Kim; Mahapatra, R.N.; Ilhyun Park; Kiyoung Choi
- Low-Power Programmable FPGA Routing Circuitry
Anderson, J.H.; Najm, F.N.
- Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs
Jie Gu; Harjani, R.; Kim, C.H.
- Wire Topology Optimization for Low Power CMOS
Zuber, P.; Bahlous, O.; Ilnseher, T.; Ritter, M.; Stechele, W
- Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique
Leary, G.; Srinivasan, K.; Mehta, K.; Chatha, K.S.
- Vibration-to-electric energy conversion
Meninger, S.; Mur-Miranda J.O.; Amirtharajah, R.; Chandrakasan A.; Lang, J.H.
- Floating-Point FPGA: Architecture and Modeling
Chun Hok Ho; Chi Wai Yu; Leong, P.; Luk, W.; Wilton, S.
- Performance-Oriented Parameter Dimension Reduction of VLSI Circuits
Zhuo Feng; Peng Li
- Design and Analysis of Two Low-Power SRAM Cell Structures
Razavipour, G.; Afzali-Kusha, A.; Pedram, M.
- "A survey of design techniques for system-level dynamic power
Benini, L; Bogliolo, A; De Micheli, G;
- An Energy and Performance Exploration of Network-on-Chip Architectures
Banerjee, A.; Wolkotte, P.T.; Mullins, R.D.; Moore, S.W.; Smit, G.J.M.
- Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension
Benkrid, Abd.S.; Benkrid, K.
- A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations
Paul, S. Jayakumar, N. Khatri, S.P.
- 3-D Topologies for Networks-on-Chip
Pavlidis, V.F.; Friedman, E.G.