Top 25 Downloaded Manuscripts - 2008
- System Architecture and Implementation of MIMO Sphere Decoders on FPGA
Xinming Huang; Cao Liang; Jing Ma
- Design of ultrahigh-speed low-voltage CMOS CML buffers and latches
Heydari, P.; Mohanavelu, R.
- The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies
Agarwal, K.; Nassif, S.
- Fast Elliptic Curve Cryptography on FPGA
Chelton, W.N.; Benaissa, M.
- A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors
Beckett, P.
- A Power-Efficient and Self-Adaptive Prediction Engine for H.264/AVC Decoding
Ke Xu; Chiu-Sing Choy
- Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware
Rauwerda, G.K.; Heysters, P.M.; Smit, G.J.M.
- Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective
Gogniat, G.; Wolf, T.; Burleson, W.; Diguet, J.-P.; Bossuet, L.; Vaslin, R.
- FPGA Implementation(s) of a Scalable Encryption Algorithm
Mace, F.; Standaert, F.-X.; Quisquater, J.-J.
- Characterization of a Novel Nine-Transistor SRAM Cell
Zhiyu Liu; Kursun, V.
- A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic
Chua-Chin Wang; Chi-Chun Huang; Ching-Li Lee; Tsai-Wen Cheng
- A survey of design techniques for system-level dynamic power management
Benini, L.; Bogliolo, A.; De Micheli, G.
- A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Myjak, M.J.; Delgado-Frias, J.G
- Body Bias Voltage Computations for Process and Temperature Compensation
Kumar, S.V.; Kim, C.H.; Sapatnekar, S.S.
- The Reconfigurable Instruction Cell Array
Khawam, S.; Nousias, I.; Milward, M.; Ying Yi; Muir, M.; Arslan, T.
- Applying CDMA Technique to Network-on-Chip
Xin Wang; Tapani Ahonen; Jari Nurmi
- Reconfigurable Architecture for Network Flow Analysis
Yusuf, S.; Luk, W.; Sloman, M.; Dulay, N.; Lupu, E.C.; Brown, G.
- Optimal Overlapped Message Passing Decoding of Quasi-Cyclic LDPC Codes
Yongmei Dai; Zhiyuan Yan; Ning Chen
- Write Disturbance Modeling and Testing for MRAM
Chin-Lung Su; Chih-Wea Tsai; Cheng-Wen Wu; Chien-Chung Hung; Young-Shying Chen; Ding-Yeong Wang; Yuan-Jen Lee; Ming-Jer Kao
- Architectural Modifications to Enhance the Floating-Point Performance of FPGAs
Beauchamp, M.J.; Hauck, S.; Underwood, K.D.; Hemmert, K.S.
- Low Power Design of Precomputation-Based Content-Addressable Memory
Shanq-Jang Ruan; Chi-Yu Wu; Jui-Yuan Hsieh
- Vibration-to-electric energy conversion
Meninger, S.; Mur-Miranda, J.O.; Amirtharajah, R.; Chandrakasan, A.; Lang, J.H.
- Achieving Programming Model Abstractions for Reconfigurable Computing
Andrews, D.; Sass, R.; Anderson, E.; Agron, J.; Peck, W.; Stevens, J.; Baijot, F.; Komp, E.
- High-throughput LDPC decoders
Mansour, M.M.; Shanbhag, N.R.
- Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating
Singh, H.; Agarwal, K.; Sylvester, D.; Nowka, K.J.