Editor-in-Chief
Associate Editor-in-Chief
Massimo Alioto
Department of Electrical and Computer Engineering
National University of Singapore
Singapore 117583
malioto@ieee.org
Ultra-low voltage digital circuits; Self-powered integrated systems; Approximate computing; Near-threshold processors, memories and specialized hardware; Emerging technologies
Associate Editor
Bevan Baas
Dept. of Electrical and Computer Engineering
University of California
Davis, CA 95616-5294
bbaas@ucdavis.edu
Many-core processors; DSP algorithms and architectures; Video and image processors; Programmable DSP architectures; Embedded processors
Associate Editor
Chye Chirin Boon
Nanyang Technological Univ.
Singapore
ECCBoon@ntu.edu.sg
RF Receiver; RF Transmitter; Phase-locked Loop (PLL); Wireless IC; MMW IC
Associate Editor
Chip-Hong Chang
School of Electrical and Electronic Engineering
Nanyang Technological University
Singapore
ECHChang@ntu.edu.sg
Residue Number Systems; Computer Arithmetic; Physical Unclonable Functions; Hardware Trojan Detection; Hardware Security
Associate Editor
Meng-Fan (Marvin) Chang
Department of Electrical Engineering
National Tsing Hua University
Hsinchu, 30013
Taiwan
mfchang@ee.nthu.edu.tw
Memory circuits; Ultra low-voltage designs; Nonvolatile logics and processors; Computing-in-memory; Device and circuit interaction for emerging devices
Associate Editor
Naeuhyuck Chang
Korea Advanced Institute of Science & Technology
Daejeon, 305701
Korea
naehyuck@cad4x.kaist.ac.kr
System-level power estimation; Low-power system design; Embedded systems; Design automation of things; Energy harvesting systems
Associate Editor
Shih-Chieh Chang
Department of Computer Science
National Tsing Hua University
Taiwan 30013, R.O.C.
scchang@cs.nthu.edu.tw
Synthesis; Low power; Adaptive architecture
Associate Editor
Yao-Wen Chang
Department of Electrical Engineering
National Taiwan University
Taipei, 10615
Taiwan
ywchang@ntu.edu.tw
Physical Design; Design for Manufacturability/Reliability; Analog Layout Design Automation; Package, Board, and Chip Design/Co-Design; Low Power Design
Associate Editor
Poki Chen
Department of Electronic Engineering
National Taiwan University of Science and Technology
Taipei, Taiwan, R.O.C.
poki@mail.ntust.edu.tw
Smart temperature sensor; Time-to-digital converter; Digital-to-time converter; Phase-locked loop; Delay-locked loop
Associate Editor
Masud Chowdhury
Department of Computer Science and Electrical Engineering
University of Missouri
Kansas City, MO 64110-2499
masud@umkc.edu
On-chip Voltage Regulation; Subthreshold Design for Ultra Low Power Circuits; Noise, Timing, and Power Issues; 3D Integrated Circuits; 2D Nanomaterial based Devices and Circuits
Associate Editor
Pasquale Corsonello
Department of Informatics, Modeling, Electronics and System Engineering (DIMES)
University of Calabria
Rende, Italy
p.corsonello@unical.it
Low-Power digital circuit design; VLSI circuits for image processing; Field Programmable Gate Arrays; Quantum Dot Cellular Automata circuits and architectures
Associate Editor
Shiro Dosho
Lab. for Future Interdisciplinary Research of Science and Tech.(FIRST)
Tokyo Institute of Technology
Yokohama, 226-8503, Japan
dosho.s.aa@m.titech.ac.jp
Sensor, IoT, ADC, PLL, Mixed-Signal
Associate Editor
Rolf Drechsler
University of Bremen/DFKI
Germany
drechsler@uni-bremen.de
Verification, Formal Methods, Reversible Circuits, Reversible Computation, Emerging Technologies
Associate Editor
Ibrahim (Abe) Elfadel
Institute Center for Microsystems (iMicro)
Masdar Institute of Science and Technology
Abu Dhabi, UAE
ielfadel@masdar.ac.ae
Power/thermal management of digital systems, 3D integration, High-speed interconnect, Low-power embedded DSP, Power-source integration, VLSI CAD, sensor-based architectures, and Internet of Things
Associate Editor
Said Hamdioui
Department of Computer Engineering
Delft University of Technology
Delft, The Netherlands
S.Hamdioui@tudelft.nl
Memory test; 3D stacked IC Test; IC reliability; Memristor Technology; Hardware security
Associate Editor
Masanori Hashimoto
Department of Communications and Computer Engineering
Kyoto University
Kyoto, Japan
hashimoto@i.kyoto-u.ac.jp
Design for reliability; Timing analysis; Power integrity analysis; Low voltage design; Low power design
Associate Editor
Deukhyoun Heo
School of Electrical Engineering and Computer Science
Washington State Univ. Pullman
WA 99164-2752 USA
dheo@wsu.edu
RF/Microwave/Mm-wave Wireless Transceiver; Power management Circuits; Wireless links for intra- and inter-chip communications
Associate Editor
Tsung-Yi Ho
Dept. of Computer Science
National Chiao Tung University
Hsinchu, Taiwan 30010
tyho@cs.nctu.edu.tw
Design Automation and Optimization for Microfluidic Biochips; Automobiles; Energy Applications; Nanometer Integrated Circuits
Associate Editor
Houman Homayoun
Department of Electrical and Computer Engineering
George Mason University
Fairfax, Virginia, 22030
hhomayou@gmu.edu
Hardware Security and Trust; Big Data Computing; Heterogeneous Architectures; Biomedical Computing; Application Benchmarking and Characterization; Memory Design
Associate Editor
Yuh-Shyan Hwang
Department of Electronic Engineering
National Taipei University of Technology
Taipei, Taiwan, R.O.C.
yshwang@mail.ntut.edu.tw
Analog Ics; Mixed-signal Ics; Power management Ics; Sensor circuits; Low-voltage low-power VLSI circuits.
Associate Editor
Rajiv Joshi
IBM
Yorktown Heights, NY 10598
rvjoshi@us.ibm.com
Technology; FinFETs; Emerging devices; 3D; Variability; Reliability; VLSI Memories; SRAM; CAD aspect related to memory; Low power design; VLSI Circuits; Interconnects; Predictive Analytics
Associate Editor
Tanay Karnik
Academic Research Office
Intel Corporation
Hillsboro, OR 97124
Tanay.Karnik@intel.com
Adaptive circuits; Switching converters; Cache memories; Radiation Hardening; Physical Design
Associate Editor
Mehran Mozaffari Kermani
College of Engineering
University of South Florida
Tampa, FL 33620
mehran2@usf.edu
Hardware Security and Trust; VLSI Architectures for Computer Arithmetic; Cryptographic Hardware; Medical Devices Reliability and Security; Fault Diagnosis and Tolerance in Signal Processing
Associate Editor
Chulwoo Kim
Dept. of Electronics Engineering
Korea University
ckim@korea.ac.kr
PLL, DLL; Wireline transceiver (not wireless transceiver); Power management (DC-DC converter, LDO); ADC; Energy harvesting circuit
Associate Editor
Tony Tae-Hyoung Kim
School of Electrical and Electronic Engineering
Nanyang Technological University
Singapore 639798
thkim@ntu.edu.sg
approximate computing; ultra-low power digital circuits; ultra-low voltage circuits; memory circuits; circuit reliability
Associate Editor
Jaydeep Kulkarni
Department of Electrical and Computer Engineering
University of Texas at Austin
Austin, TX 78701
jaydeep@austin.utexas.edu
Memory; Low-voltage design; Energy-efficiency; Resiliency; Power-management
Associate Editor
Erik Larsson
Dept. of Electrical & Information Technology
Lund University
Lund, 22100 Sweden
erik.larsson@eit.lth.se
Test planning, System test, Standards for test, Fault-tolerance, Stacked chip testing
Associate Editor
Hai Li
Dept. of Electrical and Computer Engineering
Duke University
Durham, NC 27708 USA
Hai.li@duke.edu
Memory design and architecture; Neuromorphic computing; Device modeling; Low power design
Associate Editor
Huawei Li
Institute of Computing Technology, Chinese Academy of Sciences
Beijing 100190, China
lihuawei@ict.ac.cn
Digital circuit testing; Design verification; Hardware security; Design for reliability; Approximate computing
Associate Editor
Prabhat Mishra
Department of Computer & Information Science & Engineering
Univ. of Florida
Gainesville, FL 32611 USA
prabhat@cise.ufl.edu
Embedded Systems; System-level Verification; Post-Silicon Validation and Debug; Energy-aware Computing; Hardware Security and Trust
Associate Editor
Makoto Nagata
Graduate School of System Informatics
Kobe University
Kobe, Japan
nagata@cs.kobe-u.ac.jp
Mixed signal VLSI design; Hardware security; 3D IC; Power supply integrity; Electromagnetic compatibility
Associate Editor
Koji Nii
TSMC Design Technology Japan, Inc.
Yokohama 220-0012, Japan
nii.koji@gmail.com
SRAM; TCAM; ROM; Low-power; Embedded memory
Associate Editor
Partha Pande
Computer Engineering School of EECS
Washington State Univ.
Pullman, WA 99164-2752 USA
pande@eecs.wsu.edu
Network-on-Chip; Multicore; Power Management; 3D Integration; Hardware Accelerato
Associate Editor
Bipul C. Paul
GLOBALFOUNDRIES
Malta, NY 12020, USA
bipul.paul@globalfoundries.com
Low-power digital circuits; Memory, Emerging technologies, Statistical design, Design for reliability
Associate Editor
Ioannis Savidis
Department of Electrical and Computer Engineering
Drexel University
Philadelphia, PA 19104
isavidis@coe.drexel.edu
High performance digital and mixed-signal integrated circuit design; 3-D integrated circuits; Electrical and thermal modeling; Power and clock delivery; Hardware security
Associate Editor
Aida Todri-Sanial
Microelectronics Department
CNRS-LIRMM/University of Montpellier
Montpellier, France 34095
aida.todri@lirmm.fr
Physical design; Low-power design; Emerging technologies (i.e. 3D, carbon nanotubes, etc.); Device and circuit reliability; Electro-thermal simulation
Associate Editor
Mingoo Seok
Electrical Engineering
Columbia University
New York, NY 10027
ms4415@columbia.edu
Process-variation/thermal/aging adaptive circuits; Near/sub-threshold voltage circuits; Machine-learning hardware
Associate Editor
Sheldon Tan
Department of Electrical and Computer Engineering
University of California at Riverside
Riverside, CA 92521
stan@ece.ucr.edu
Analog/mixed-signal circuits; Signal/power integrity; Thermal and reliability model and optimization; Parallel analysis
Associate Editor
Mark Tehranipoor
Dept. of Electrical and Computer Engineering
University of Florida
Gainesville, FL 32611-6200
Tehranipoor@ece.ufl.edu
Hardware Security and Trust; Reliable Circuit Designs; VLSI Testing
Associate Editor
Xiaoqing Wen
Dept. of Creative Informatics
Kyushu Institute of Technology
Fukuoka 820-8502, Japan
wen@cse.kyutech.ac.jp
Power-Aware Testing; Automatic Test Pattern Generation (ATPG); Design for Testability (DFT); Fault Diagnosis; Built-In Self Test (BIST)
Associate Editor
Jiang Xu
Department of Electronic and Computer Engineering
Hong Kong University of Science and Technology
Clear Water Bay, Kowloon, Hong Kong SAR
jiang.xu@ust.hk
MPSoC; NoC; HW/SW Codesign; Optical/Photonic Interconnects; Reliability
Associate Editor
Wei Zhang
Dept. of Electronic & Computer Engineering
Hong Kong Univ. of Sci. & Technology
New Territories, Hong Kong China
wei.zhang@ust.hk
Reconfigurable computing; FPGA-based design; Thermal and power management; Electronic design automation; Emerging technologies
Associate Editor
Zhengya Zhang
Electrical Engineering and Computer Science
University of Michigan, Ann Arbor
Ann Arbor, MI 48109-2122 USA
zhengya@umich.edu
Digital communication systems,; Digital signal processing systems; Neuromorphic computing; Application-specific architecture, Error resilience
Editorial Assistant
Stacey Weber Jackson
Dept. of Electrical Engineering
Princeton University
Princeton, NJ 08544
tvlsiadm@ieee.org